Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits

Author

Beeftink, E. ; van Genderen, A.J. ; van der Meijs, N.P.

Author_Institution

Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands

fYear

1995

fDate

2-4 Oct 1995

Firstpage

360

Lastpage

365

Abstract

In this paper, we describe how we have exploited the advantages of various methods for device recognition and modeling in a layout-to-circuit extractor, called Space. Hence, we have obtained a program that, for different technologies, can quickly translate a large layout into an equivalent network. The network includes layout parasitics of the interconnects and can directly be simulated by various simulation packages, such as Spice. The efficiency and accuracy of the extractor are confirmed by experimental results and enable a fast and reliable layout verification for both MOS and bipolar/BiCMOS technologies

Keywords

BiCMOS integrated circuits; MOS integrated circuits; bipolar integrated circuits; circuit analysis computing; circuit layout CAD; Space; Spice; bipolar/BiCMOS integrated circuits; device modeling; device recognition; equivalent network; high-speed MOS integrated circuits; interconnects; layout parasitics; layout-to-circuit extraction; BiCMOS integrated circuits; Bipolar integrated circuits; Capacitance; Fabrication; Integrated circuit interconnections; Integrated circuit layout; Integrated circuit technology; MOS devices; Packaging; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1995. ICCD '95. Proceedings., 1995 IEEE International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-8186-7165-3

Type

conf

DOI

10.1109/ICCD.1995.528834

Filename

528834