Title :
Switch-level delay test of domino logic circuits
Author :
Natarajan, Suriyaprakash ; Gupta, Sandeep K. ; Breuer, Melvin A.
Author_Institution :
EE-Systems, Univ. of Southern California, Los Angeles, CA, USA
Abstract :
We address the testing of delay faults in domino circuits that contain complex gates. The different ways in which these faults can cause errors are demonstrated. We identify structures in both the evaluate and the precharge logic that should be tested for delay faults. We propose conditions to generate delay tests for them, and outline extensions to handle mixed static-domino circuits. Testability results are reported for benchmark circuits that are mapped to domino gates and in-house domino circuits
Keywords :
CMOS logic circuits; delay estimation; integrated circuit testing; logic testing; complex gates; delay faults; delay test methodology; domino CMOS logic gates; domino logic circuits; errors; mixed static-domino circuits; precharge logic; switch-level delay test; testability; CMOS logic circuits; Circuit faults; Circuit testing; Delay; Logic circuits; Logic gates; Logic testing; Robustness; Semiconductor device modeling; Switching circuits;
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-7169-0
DOI :
10.1109/TEST.2001.966653
