Test path simulation and characterisation

Interfacing DUTs and ATE for testing at clock rates in the high hundreds of MHz with timing accuracy constraints of a few ten picoseconds and high pin count or high parallelism requirements significantly increases device interface development efforts. Current device interface design, manufacturing and test methods are no longer sufficient and contribute to rising test costs. This paper describes an approach to achieve appropriate device interface performance under high data rate/high pin count requirements, applying a combination of measurement and virtual test techniques to device interface development