Field isolation for the Gigabit era devices

Author

Deleonibus, S.

Author_Institution

Dept. de Microelectron., CEA, Grenoble, France

fYear

1993

fDate

13-16 Sept. 1993

Firstpage

391

Lastpage

398

Abstract

Field isolation for Ultra Large Scale Integration devices is evolving towards product adapted architectures. Specific solutions can be used for memory or bipolar devices that we distinguish from standard logic CMOS/BiCMOS devices for which Poly Buffer LOCOS, SILO and shallow trench isolations are taken as examples.

Keywords

ULSI; bipolar integrated circuits; isolation technology; logic circuits; oxidation; semiconductor storage; SILO; bipolar device memory; field isolation; gigabit era devices; poly buffer LOCOS; shallow trench isolation; ultra large scale integration device; BiCMOS integrated circuits; CMOS logic circuits; Degradation; EPROM; Etching; Logic devices; Oxidation; Temperature; Ultra large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 1993. ESSDERC '93. 23rd European

Conference_Location

Grenoble

Print_ISBN

2863321358

Type

conf

Filename

5435529

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1913699