Test challenges for SONET/SDH physical layer OC3 devices and beyond

Testing SONET/SDH physical layer devices at and above OC3 (optical carrier 3)/STS3 (synchronous transport signal 3) rates needs a new approach. Due to fast edge rates the spectral content of the signals is in the GHz range. High speed transceivers must have low voltage differential I/O to meet fast data transfer rates over longer transmission lines. Such devices with high pin count and data rates above OC3/STS3 are sensitive to pin to pin skew on the Automatic Test Equipment (ATE). Many factors have to be taken into account during test development phase to capture and test the above signal conditions. Transmission line effects are one of the key parameters to be accounted for load board design. Test instrumentation and their limitations are another important resource. With technology improvements in CMOS design, mass production of high speed devices will happen in the immediate future. The following paper discusses challenges in production test of a OC3/STS3 physical layer device. ATE requirements for future higher speed devices at OC12/48/192 rates are discussed to overcome the limitations faced during test development of the OC3/STS3 device