Verification of Ethernet IP Core MAC Design Using Deterministic Test Methodology

The subject paper proposes an approach to developing a design verification environment targeted towards complex application-specific integrated circuits (ASICs), with particular emphasis on embedded systems incorporating intellectual property (IP) cores. An emergent trend seems to realize this through the use of coverage-driven functional verification (CDV) and reuse methodology (RM). The CDV relies on the ASIC functionalities and the verification process is formalized in the early stages of the design cycle. The deterministic testing together with the CDV and RM is applied in the paper to specifically verify the design of Ethernet IP MAC cores from open cores The Specman Elite e-language originally developed by Cadence is utilized in the process as the verification tool on representative IP core design implementations.