Tailoring ATPG for embedded testing

Author

Dorsch, Rainer ; Wunderlich, Hans-Joachim

Author_Institution

Stuttgart Univ., Germany

fYear

2001

fDate

2001

Firstpage

530

Lastpage

537

Abstract

An automatic test pattern generation (ATPG) method is presented for a scan-based test architecture which minimizes ATE storage requirements and reduces the bandwidth between the automatic test equipment (ATE) and the chip under test. To generate tailored deterministic test patterns, a standard ATPG tool performing dynamic compaction and allowing constraints on circuit inputs is used. The combination of an appropriate test architecture and the tailored test patterns reduces the test data volume up to two orders of magnitude compared with standard compacted test sets

Keywords

automatic test equipment; automatic test pattern generation; integrated circuit testing; software tools; ATE storage requirements; ATE-DUT bandwidth reduction; ATPG; ATPG tailoring; automatic test pattern generation method; chip under test; circuit input constraints; dynamic compaction; embedded testing; scan-based test architecture; standard ATPG tool; standard compacted test sets; systems-on-a-chip; tailored deterministic test patterns; tailored test patterns; test architecture; test data volume; test resource partitioning; Automatic test pattern generation; Automatic testing; Bandwidth; Built-in self-test; Circuit testing; Design automation; Pins; System testing; System-on-a-chip; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2001. Proceedings. International

Conference_Location

Baltimore, MD

ISSN

1089-3539

Print_ISBN

0-7803-7169-0

Type

conf

DOI

10.1109/TEST.2001.966671

Filename

966671