An efficient method for placement of VLSI designs with Kohonen map

In this paper a Kohonen map-based algorithm for the placement of gate arrays and standard cells is presented. An abstract specification of the design is converted to a set of appropriate input vectors using a mathematical method, called “multidimensional scaling”. These vectors which have, in general, higher dimensionality are fed to the self-organizing map at random in order to map them onto a 2D plane of the regular chip. The mapping is done in such a way that the cells with higher connectivity are placed close to each other, hence minimizing total connection length in the design. Two processes, called reassignment and rearrangement, are employed to make the algorithm applicable to the standard cell designs. In addition to the small examples introduced in other papers, two standard cell benchmarks were tried and better results were observed for these large designs compared to other neural net-barred approaches