• DocumentCode
    1914266
  • Title

    Drain current model for junctionless nanowire transistors

  • Author

    Trevisoli, Renan Doria ; Doria, Rodrigo Trevisoli ; De Souza, Michelly ; Pavanello, Marcelo Antonio

  • Author_Institution
    Lab. de Sist. Integraveis, Univ. of Sao Paulo, Sao Paulo, Brazil
  • fYear
    2012
  • fDate
    14-17 March 2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Junctionless Nanowire Transistors (JNT) are considered as promising devices for sub-20 nm era due to the great scalability they provide. This work proposes a physically based analytical model for the drain current in JNTs. The proposed model is continuous from the subthreshold region to the saturation. The model is validated with 3D TCAD simulation and experimental results.
  • Keywords
    nanowires; technology CAD (electronics); transistors; 3D TCAD simulation; analytical model; drain current model; junctionless nanowire transistor; Data models; Electric potential; Logic gates; Neodymium; Silicon; Solid modeling; Transistors; Drain Current Model; Junctionless Devices;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Devices, Circuits and Systems (ICCDCS), 2012 8th International Caribbean Conference on
  • Conference_Location
    Playa del Carmen
  • Print_ISBN
    978-1-4577-1116-9
  • Electronic_ISBN
    978-1-4577-1115-2
  • Type

    conf

  • DOI
    10.1109/ICCDCS.2012.6188924
  • Filename
    6188924
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1914266