Title :
Exact path delay grading with fundamental BDD operations
Author :
Padmanaban, S. ; Michael, M. ; Tragoudas, S.
Author_Institution :
ECE Dept., Southern Illinois Univ., Carbondale, IL, USA
Abstract :
Formulates the fault grading problem as a combinatorial problem that amounts to storing and manipulating sets on a special type of binary decision diagrams (BDDs), called zero-suppressed BDDs (ZBDDs), that represent sets in a unique and compact manner. A simple modification of the basic scheme allows us to overcome memory problems that may arise by complex set representation. Experimental results on the ISCAS´85 benchmarks show considerable improvement over all existing techniques for exact PDF grading. The main advantages of the proposed methodology are the simplicity of the approach, in terms of it being expressed by a polynomial number of increasingly efficient BDD-based operations, its organization, and its ability to handle very large test sets
Keywords :
automatic test pattern generation; binary decision diagrams; combinational circuits; delays; fault simulation; integrated circuit testing; logic simulation; logic testing; ISCAS´85 benchmarks; PDF grading; combinational circuits; combinatorial problem; exact path delay grading; fault grading problem; fundamental BDD operations; path delay fault; polynomial number; test sets; zero-suppressed BDDs; Binary decision diagrams; Boolean functions; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Data structures; Delay; Polynomials; Timing;
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-7169-0
DOI :
10.1109/TEST.2001.966684