Title :
Scan array solution for testing power and testing time
Author :
Xu, Lei ; Sun, Yihe ; Chen, Hongyi
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
Details a novel power estimation algorithm based on rate of bit propagation (RBP). Considering the reduction of RBP an advanced scan array architecture is proposed in which a wrapper and two dimensional scan chain is adopted. Estimated results based on RBP and experimental results of industrial circuits both show that testing power was reduced to the level of the functional power. Furthermore pseudo-BIST is integrated with the wrapper to reduce the test time
Keywords :
CMOS digital integrated circuits; VLSI; automatic test pattern generation; boundary scan testing; built-in self test; design for testability; integrated circuit testing; logic testing; CMOS; RBP; design for testability; digital integrated circuits; functional power; industrial circuits; power estimation algorithm; pseudo-BIST; rate of bit propagation; scan array architecture; scan array solution; test time; testing power; testing time; two dimensional scan chain; wrapper; Capacitance; Circuit testing; Energy consumption; Frequency; Partial discharges; Registers; Strontium; Sun; Switching circuits; System testing;
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-7169-0
DOI :
10.1109/TEST.2001.966685
