• DocumentCode
    1914521
  • Title

    A self-timed redundant-binary number to binary number converter for digital arithmetic processors

  • Author

    Wey, Chin-Long ; Wang, Haiyan ; Wang, Cheng-Ping

  • Author_Institution
    Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
  • fYear
    1995
  • fDate
    2-4 Oct 1995
  • Firstpage
    386
  • Lastpage
    391
  • Abstract
    This paper presents a self-timed converter circuit which converts an n-digit redundant binary number to an (n+1)-bit binary number. Self-timed refers to the fact that the conversion is problem-dependent and requires variable conversion time to complete the operation. The propagation delay of the proposed converter circuit does not increase with the number of digits to be converted, but it is determined by the maximum number of consecutive 0´s in that number. This study shows that the statistical upper bound of the average maximum number of consecutive 0´s is log3n, or 3.78 for 64-digits. This implies that the proposed self-time circuit can be approximately 17 times faster than the ripple-type converter. Thus the proposed converter is well-suited to high-speed, long-word digital arithmetic processors
  • Keywords
    convertors; delays; digital arithmetic; redundant number systems; digital arithmetic processors; propagation delay; self-timed converter circuit; self-timed redundant-binary number to binary number converter; statistical upper bound; variable conversion time; Adders; Circuits; Digital arithmetic; Hardware; Mathematics; Memory; Propagation delay; Upper bound;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1995. ICCD '95. Proceedings., 1995 IEEE International Conference on
  • Conference_Location
    Austin, TX
  • ISSN
    1063-6404
  • Print_ISBN
    0-8186-7165-3
  • Type

    conf

  • DOI
    10.1109/ICCD.1995.528838
  • Filename
    528838