Analog performance of asymmetric self-cascode p-channel fully depleted SOI transistors

Author

De Souza, Michelly ; Pavanello, Marcelo Antonio ; Flandre, Denis

Author_Institution

Dept. of Electr. Eng., Centro Univ. da FEI, São Bernardo do Campo, Brazil

fYear

2012

fDate

14-17 March 2012

Firstpage

1

Lastpage

4

Abstract

This work presents an analysis of the analog performance of asymmetric threshold voltage self-cascode fully depleted (FD) p-type SOI transistors. The experimental results showed that this structure is able to improve the devices transconductance and output conductance, resulting in increased intrinsic voltage gain and breakdown voltage in comparison to single transistors and the conventional symmetric self-cascode.

Keywords

semiconductor device models; silicon-on-insulator; transistors; analog performance; asymmetric self-cascode p-channel; asymmetric threshold voltage; breakdown voltage; fully depleted SOI transistor; intrinsic voltage gain; output conductance; p-type SOI transistor; transconductance; Current measurement; Logic gates; Periodic structures; Threshold voltage; Transconductance; Transistors; Voltage measurement; Analog Parameters; MOSFET; Self-Cascode Transistor; Silicon-On-Insulator;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems (ICCDCS), 2012 8th International Caribbean Conference on

Conference_Location

Playa del Carmen

Print_ISBN

978-1-4577-1116-9

Electronic_ISBN

978-1-4577-1115-2

Type

conf

DOI

10.1109/ICCDCS.2012.6188932

Filename

6188932