Tester retargetable patterns

Author

Kapur, Rohit ; Williams, T.W.

fYear

2001

fDate

2001

Firstpage

721

Lastpage

727

Abstract

The industry is scrambling to prevent a potential explosion in nanometer technology test cost where the cost to test a device is closing in on the cost to manufacture it. Across the test industry, entire methodologies are being readdressed, tester costs are being scrutinized, and test vector count is being reduced. In this paper, a new concept is presented that allows for lowering the cost of test by utilizing the tester resources more efficiently. The solution presented brings together an existing concept of being able to reconfigure scan chains with methods that allow the same test pattern data to be applicable for all configurations. A data model is created to emphasize the use of such technology. The concepts developed in this paper are compatible with other test cost reduction methods

Keywords

automatic test pattern generation; built-in self test; design for testability; integrated circuit economics; integrated circuit testing; ATPG; BIST; DFT; data model; nanometer technology test cost; retargetable test pattern technology; scan chain reconfigurability; test cost reduction; test pattern data; test vector count; Costs; Design for testability; Environmental economics; Explosions; Industrial economics; Manufacturing industries; Nanoscale devices; Silicon; Stress; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2001. Proceedings. International

Conference_Location

Baltimore, MD

ISSN

1089-3539

Print_ISBN

0-7803-7169-0

Type

conf

DOI

10.1109/TEST.2001.966693

Filename

966693