Systematic modeling and parameter extraction for on-chip inductors in CMOS technology

This paper presents a systematic methodology for characterizing and modeling on-chip inductors over a lossy substrate directly from S-parameter measurements. The model implementation neither requires precise knowledge of geometry or fabrication process. This eases the representation of inductors in SPICE-like simulators at high frequencies. Excellent model-experiment correlation is achieved up to 12 GHz for the circuit network parameters as well as for the Q-factor.