Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment

Author

Vollrath, Joerg ; Rooney, Randall

fYear

2001

fDate

2001

Firstpage

768

Lastpage

775

Abstract

Bit fail maps of semiconductor memories are generated in a manufacturing environment during wafer test to identify process problems and for repair. Since bit fail map capabilities are expensive for high-speed testers and massive parallel test systems, component test is generating only pass/fail information. It is difficult to relate the pass/fail information to a process problem. This paper presents a test strategy and a software tool to construct pseudo bit fail maps from pass/fail information using a special test sequence. The pseudo bit fail map can be generated in a manufacturing environment and can be used for identifying process problems and doing physical failure analysis at the fail location

Keywords

automatic test software; built-in self test; failure analysis; integrated circuit testing; integrated memory circuits; production testing; random-access storage; BIST situation; RAMs; bit fail map compression scheme; burn-in; component test; fail string analysis; manufacturing environment; pass/fail information; physical failure analysis; process problem identification; pseudo fail bit map generation; semiconductor memories; software tool; test sequence; test strategy; Costs; Failure analysis; Manufacturing processes; Production; Random access memory; Semiconductor device manufacture; Semiconductor device testing; Semiconductor memory; System testing; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2001. Proceedings. International

Conference_Location

Baltimore, MD

ISSN

1089-3539

Print_ISBN

0-7803-7169-0

Type

conf

DOI

10.1109/TEST.2001.966698

Filename

966698