Experiments with gate oxide scaling from 4.5nm down to 2.5nm for boosting CMOS performances

Author

Josse, E. ; Gowziecki, R. ; Alieu, J. ; Mourrain, C. ; Havond, D. ; Halimaoui, A. ; Martin, F. ; Skotnicki, T.

Author_Institution

France Telecom, Meylan, France

fYear

1998

fDate

8-10 Sept. 1998

Firstpage

364

Lastpage

367

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 1998. Proceeding of the 28th European

Conference_Location

Bordeaux, France

Print_ISBN

2-86332-234-6

Type

Filename

1503564

Link To Document