Cost evaluation of coverage directed test generation for the IBM mainframe

Test generation and simulation tools have input stimuli that can direct them to cover specific events. However, the cost of completely covering a verification plan is still very high. While coverage analysis tools can find events that have not been covered, they do not provide an automated covering method. This paper presents the first implementation of a generation framework that uses feedback from coverage analysis to direct microarchitecture simulation. This framework uses a coverage analysis tool to find events that have not been simulated and then utilizes information about the design to determine which directives should be given to the simulation environment. This paper describes, in detail, the system and its operation process, an experiment that uses the system, and the results of the experiment. This system was shown to reduce the machine time and person time required to cover the test plan. Implications of this work suggest the types of verification plans appropriate for the utilization of this system and the further experiments and developments required