Identifying redundant gate replacements in verification by error modeling

This paper considers verification of combinational circuits by test vectors under assumption of gate and wire replacement faults. Identifying redundant faults is critical to the quality and speed of such verification schemes. We propose the first known exact redundancy identification of gate replacement faults, together with its efficient approximations. While both solutions use the SAT formulation of redundancy identification, we propose the means to effectively use any single stuck-at-value redundancy identification in the approximate schemes, with varying detection accuracy. Critical to the latter are the novel uses of don´t care approximations that detect many redundant faults and quickly identify those that can be detected by methods for stuck-at value faults. A test generation scheme that uses the error-correcting properties of Arithmetic Transforms is incorporated into the overall verification procedure, and is shown to provide high fault coverage for these fault models