Path Optimization Protocol Based on Speed Low Power Metrics

Author

Verle, A. ; Landrault, A. ; Maurine, P. ; Azemard, N.

Author_Institution

Montpellier Lab. of Comput. Sci., Robotics, & Microelectron., UMR CNRS/Universite de Montpellier II

Volume

1

fYear

2005

fDate

21-24 Nov. 2005

Firstpage

523

Lastpage

526

Abstract

The design of high performance circuits implies to manage CAD tools with physical level defined indicators. In this paper, we validate a design space exploration method, defining maximum and minimum delay bounds on logical paths. Then we adapt this method to a "constant sensitivity method" allowing to size a circuit at minimum area under a delay constraint. Three techniques are characterized: path global sizing, local buffer insertion and mixed sizing and buffer insertion. These methods are implemented in an optimization tool and compared on ISCAS\´85 benchmarks with an industrial tool

Keywords

buffer circuits; circuit CAD; logic design; protocols; sensitivity analysis; CAD tools; ISCAS´85 benchmarks; constant sensitivity; design space exploration; high performance circuits; local buffer insertion; logical paths; path global sizing; path optimization protocol; speed low power metrics; Circuits; Computer science; Delay effects; Energy management; Laboratories; Logic gates; Microelectronics; Optimization methods; Protocols; Timing; Buffer insertion; delay constraint; gate sensitivity; path performance optimization; sizing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer as a Tool, 2005. EUROCON 2005.The International Conference on

Conference_Location

Belgrade

Print_ISBN

1-4244-0049-X

Type

conf

DOI

10.1109/EURCON.2005.1629980

Filename

1629980