Test evaluation and data on defect-oriented BIST architecture for high-speed PLL

Author

Kim, Seongwon ; Soma, Mani

Author_Institution

Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA

fYear

2001

fDate

2001

Firstpage

830

Lastpage

837

Abstract

Experimental results are presented for the defect-oriented testing of PLLs using the charge-based frequency measurement BIST technique. Using National Semiconductor Corp.´s 0.25 μm CMOS 900 MHz PLL, we demonstrate a low-cost and practical BIST solution. The area overhead is minimized by using the existing PLL circuitry for the BIST structure. The test time is typically 12 μsec, significantly faster than conventional testing

Keywords

CMOS analogue integrated circuits; Monte Carlo methods; built-in self test; fault simulation; high-speed integrated circuits; integrated circuit testing; mixed analogue-digital integrated circuits; phase locked loops; 0.25 micron; 12 mus; 900 MHz; CMOS PLL; Monte-Carlo analysis; National Semiconductor; area overhead minimization; charge-based frequency measurement BIST technique; defect-oriented BIST architecture; low-cost practical BIST solution; mixed-signal ICs; test evaluation; test time; Built-in self-test; Circuit faults; Circuit testing; Cost function; Frequency measurement; Impedance; Integrated circuit testing; Manufacturing; Phase locked loops; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2001. Proceedings. International

Conference_Location

Baltimore, MD

ISSN

1089-3539

Print_ISBN

0-7803-7169-0

Type

conf

DOI

10.1109/TEST.2001.966705

Filename

966705