A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line

In recent years, much effort has been placed on improving the performance of timing and jitter measurement devices using Delay Locked Loop (DLL) and Vernier Delay Line (VDL) techniques. However, these approaches require highly matched elements in order to reduce differential nonlinearity timing errors. In an attempt to reduce the requirement on element matching, a component-invariant VDL technique is proposed that will enable the measurement device to be synthesized from a register transfer level (RTL) description. Furthermore, as test time is an important consideration during a production test, a method is provided that reduces test time at the expense of more hardware. Experimental results on an FPGA implementation are provided as proof of concept. An IC prototype has also been designed and submitted for fabrication. Implementation details are provided in this paper