Title :
A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line
Author :
Chan, Antonio H. ; Roberts, Gordon W.
Author_Institution :
Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada
Abstract :
In recent years, much effort has been placed on improving the performance of timing and jitter measurement devices using Delay Locked Loop (DLL) and Vernier Delay Line (VDL) techniques. However, these approaches require highly matched elements in order to reduce differential nonlinearity timing errors. In an attempt to reduce the requirement on element matching, a component-invariant VDL technique is proposed that will enable the measurement device to be synthesized from a register transfer level (RTL) description. Furthermore, as test time is an important consideration during a production test, a method is provided that reduces test time at the expense of more hardware. Experimental results on an FPGA implementation are provided as proof of concept. An IC prototype has also been designed and submitted for fabrication. Implementation details are provided in this paper
Keywords :
CMOS logic circuits; application specific integrated circuits; calibration; delay lines; electric variables measurement; field programmable gate arrays; integrated circuit testing; logic testing; timing; CMOS process; IC prototype; RTL description; calibration; component-invariant technique; differential nonlinearity timing errors; high-resolution timing measurement device; production test; register transfer level description; test time; vernier delay line technique; Circuit testing; Clocks; Counting circuits; Delay lines; Field programmable gate arrays; Performance evaluation; Phase measurement; Propagation delay; Ring oscillators; Timing jitter;
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-7169-0
DOI :
10.1109/TEST.2001.966708
