Title :
A new multiple weight set calculation algorithm
Author :
Hong-Sik Kirn ; Lee, Jin-kyue ; Kang, Sungho
Author_Institution :
Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea
Abstract :
The number of weighted random patterns depends on the sampling probability of the corresponding deterministic test pattern. Therefore if the weight set is extracted from the deterministic pattern set with high sampling probabilities, the test length can be shortened. In this paper we present a new multiple weight set generation algorithm that generates high performance weight sets by removing deterministic patterns with low sampling probabilities. In addition, the weight set that makes the variance of sampling probabilities for deterministic test patterns small, reduces the number of the deterministic test patterns with low sampling probability. Henceforth we present a new weight set calculation algorithm that uses the optimal candidate list and reduces the variance of the sampling probability. The results on ISCAS 85 and ISCAS 89 benchmark circuits prove the effectiveness of the new weight set calculation algorithm
Keywords :
VLSI; automatic test pattern generation; built-in self test; design for testability; integrated circuit testing; logic testing; probability; ATPG; BIST pattern generator; DFT technique; VLSI circuits; built-in self test; deterministic test pattern; high performance weight sets; multiple weight set calculation algorithm; multiple weight set generation algorithm; sampling probability; test length reduction; weighted random patterns; Automatic test pattern generation; Built-in self-test; Circuit faults; Circuit testing; Design for testability; Logic testing; Probabilistic logic; Probability; Sampling methods; Test pattern generators;
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-7169-0
DOI :
10.1109/TEST.2001.966710
