DocumentCode
1915291
Title
SOI Technology Outlook for Sub-0.25 μm CMOS, Challenges and Opportunities
Author
Davari, Bijan ; Shahidi, Ghavam G.
Author_Institution
Semicond. R&D Center (SRDC), T.J. Watson Res. Center, IBM, Yorktown Heights, NY, USA
fYear
1993
fDate
13-16 Sept. 1993
Firstpage
669
Lastpage
674
Abstract
In this paper, the outlook for the SOI technology in the sub-0.25 μm CMOS regime is discussed. The key challenges and opportunities for the SOI technology on the road to becoming a main stream semiconductor technology are presented.
Keywords
CMOS integrated circuits; silicon-on-insulator; CMOS regime; SOI technology; semiconductor technology; CMOS technology; Costs; Delay; Implants; Isolation technology; Substrates; Temperature; Thermal conductivity; Thickness control; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1993. ESSDERC '93. 23rd European
Conference_Location
Grenoble
Print_ISBN
2863321358
Type
conf
Filename
5435585
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