Analysis of Carrier Transport and Heating in Ultra-Small SOI N-MOSFETs

Device simulation is adopted to investigate the main implications of scaling SOI MOSFETs to gate length well below 0.1μm. Effects of the reduction of silicon layer thickness and of the back oxide thickness are discussed. Reduction of the silicon layer thickness is effective in suppressing short channel effects (SCE) by ensuring better gate control of the back interface. Furthermore, the results of Monte Carlo simulations predict, in agreement with recent experiments, a decrease of hot carrier effects. On the other hand, by reducing the silicon layer thickness, an increase of the carrier transit time may be expected.