A Clock Gating Circuit for Globally Asynchronous Locally Synchronous Systems

This paper proposes a circuit that enables the use of off-chip oscillators in a globally asynchronous locally synchronous system. Usually, a local oscillator is used, which can be stopped. However, a local oscillator, e.g., ring oscillator, is not as stable as an off-chip oscillator and is therefore problematic to use for certain applications. The proposed circuit also informs the local synchronous module if the local clock has been stopped for too many of the off-chip oscillators clock cycles, so that it can take appropriate actions, e.g., recalibrate ring oscillators. The circuit has been tested in an Altera Stratix II FPGA and simulated in a 0.35 mum CMOS process