BIST and fault insertion re-use in telecom systems

This paper describes a comprehensive off-line system level test strategy developed for several complex high speed, telecom chips. These chips feature a large number of clocks, mixed analog and digital logic and large high speed RAMs. The test strategy was based on the principles of hierarchical test, DFT reuse, BIST and at-speed test, and was implemented using DFT solutions provided by Logic Vision. The paper further specifies the requirements for integration of the DFT solutions within the ASIC vendor´s flow. The final DFT implementation which includes scan, at-speed Logic BIST, RAM BIST, PLL BIST, user-defined IEEE 1149.1 TAP and Boundary Scan with fault insertion capability, is presented The system level test architecture focusing on an in-house developed TAP Master is given. Motivation from a cost saving perspective in system SW development and improved system quality monitoring are highlighted as major driving forces in support of this strategy. Finally, some practical issues for consideration when planning system test based on BIST are presented