DocumentCode :
1915695
Title :
An evaluation of defect-oriented test: WELL-controlled low voltage test
Author :
Sato, Yasuo ; Kohno, Masaki ; Ikeda, Toshio ; Yamazaki, Iwao ; Hamamoto, Masato
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
fYear :
2001
fDate :
2001
Firstpage :
1059
Lastpage :
1067
Abstract :
This paper presents an evaluation of defect-oriented test that targets bridging defects or leakage defects in the deep sub-micron process. As the power supply voltage or the threshold voltage (Vt) decreases, the detection of these defects becomes more difficult. Therefore the effectiveness of each test method should be clarified. In this paper we newly propose the WELL-controlled low voltage (WLV) test, which is a low-voltage test with substrate back biasing, and prove that it detects the defects that are not detected by the IDDQ test. The effectiveness of the WLV test for a small gate-width circuit is also discussed for a noisy environment when the very-low-voltage (VLV) test is inapplicable
Keywords :
VLSI; integrated circuit testing; leakage currents; sensitivity analysis; WELL-controlled LV test; bridging defects; deep submicron process; defect-oriented test; delta IDDQ technique; leakage defects; low-voltage test; noisy environment; power supply voltage reduction; sensitivity evaluation; small gate-width circuit; substrate back biasing; threshold voltage reduction; Circuit noise; Circuit testing; Energy consumption; Histograms; Large scale integration; Leak detection; Low voltage; Power supplies; Threshold voltage; Working environment noise;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
ISSN :
1089-3539
Print_ISBN :
0-7803-7169-0
Type :
conf
DOI :
10.1109/TEST.2001.966732
Filename :
966732
Link To Document :
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