Darlington and parallel operations in monolithically integrated BiMOS transistor chip

Darlington and parallel operations have been monolithically integrated using DMOS technology to develop a BiMOS transistor chip for superior switching speed with high current and power handling capacity for digital/analog circuitry. To achieve higher switching speed, an additional MOSFET has been integrated on the same chip and the switching time of the BiMOS transistor has been reduced to 240 ns at a collector current of 1 A. A CAD (computer-aided design) analysis has been performed using a device and circuit program to determine the interdependence of gain, transconductance, and threshold voltage with regard to channel length, base charge, oxide charge and thickness and ratio of channel width to length. To control V_T, a cleaning procedure has been developed, and it is observed that IPA rinsing results in a low C-V shift of only 33 mv, a trap charge density of 4×10¹⁰ cm²/eV, and a high dielectric strength of 8 to 12 MV/Cm