Title :
On static test compaction and test pattern ordering for scan designs
Author :
Lin, Xijiang ; Rajski, Janusz ; Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Mentor Graphics Corp., Wilsonville, OR, USA
Abstract :
A static compaction procedure to reduce test set size for scan designs and a procedure to order test patterns in order to steepen the fault coverage curve are presented. The computational effort for both procedures is linearly proportional to the computational effort required for standard fault simulation with fault dropping. Experimental results on large industrial circuits demonstrate both the efficiency and effectiveness of the proposed procedures
Keywords :
automatic test pattern generation; fault simulation; logic testing; compact test sets; deterministic ATPG tool; fault coverage; fault simulation; irredundant test sets; scan circuits; scan designs; static test compaction procedure; test pattern ordering; test set size reduction; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Compaction; Computer graphics; Costs; Design engineering; Fault detection; Test pattern generators;
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-7169-0
DOI :
10.1109/TEST.2001.966735
