DocumentCode :
1915838
Title :
Unit level predicted yield: a method of identifying high defect density die at wafer sort
Author :
Miller, Russell B. ; Riordan, Walter C.
Author_Institution :
Technol. & Manuf. Group, Intel Corp., USA
fYear :
2001
fDate :
2001
Firstpage :
1118
Lastpage :
1127
Abstract :
Previous studies have demonstrated both theoretically and empirically that defect density at wafer sort is an effective predictor of burn-in failures on packaged semiconductor devices. Therefore, efficient methods of measuring sort defect density are of great interest. This paper explores optimal methods for measuring sort defect density at the die level, as opposed to the lot or wafer level, and using this measure to screen reliability defects. The authors developed a simple measure called unit level predicted yield, based on the yield of other die in the same fab lot, and demonstrated its strong correlation to burn-in failures on packaged units. The method makes physical sense, and has been validated on more than 80 million units on three fab processes, including Intel´s 0.8 μm, 6 layer metal CMOS logic process. It is applicable to known good die programs, or anywhere that die level reliability differentiation is desirable. It is shown to be approximately twice as efficient as wafer level methods at highlighting die with high latent defect density
Keywords :
CMOS logic circuits; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; integrated circuit yield; production testing; 0.8 micron; CMOS logic process; burn in failures; defect density; die level reliability differentiation; die level sort defect density; die yield; fab lots; high defect density die; known good die programs; latent defect density; packaged semiconductor devices; reliability defect screening; unit level predicted yield; unit level predicted yield method; wafer level methods; wafer sort; wafer sort defect density; CMOS logic circuits; CMOS process; Density measurement; Measurement units; Probes; Semiconductor device manufacture; Semiconductor device packaging; Semiconductor devices; Testing; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
ISSN :
1089-3539
Print_ISBN :
0-7803-7169-0
Type :
conf
DOI :
10.1109/TEST.2001.966738
Filename :
966738
Link To Document :
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