CMOS Logic Gates Based on the Minimum Theoretical Number of Transistor in Series

The propagation delay in CMOS gates is strongly related to the number of stacked PMOS and NMOS devices in the pull-up and pull-down networks, respectively. The standard CMOS logic style is usually optimized targeting one logic plane, presenting the complemented topology in the other one. As a consequence, the minimum number of transistors in series is not necessarily achieved. In this paper is presented the method for building CMOS logic gates which respect the lower bound of transistors in series in both pull-up and pull-down planes. Then, the new CMOS gates are compared to the conventional ones through electrical characterization of a complete set of unate functions with 3- to 6-inputs. Some functions which result in more than 13 transistors in series in standard complemented topologies have been mapped to multi-gate circuits using SIS tool, and also compared to such novel approach. The results show improvements up to 45% in the average delay comparing single gates, and up to 75% in the power-delay product when comparing more complex gates to mapped circuits