An Aggressive Register-level Communication in a Speculative Chip Multiprocessor

This paper presents an enhanced version of Snoopy inter-register communication (SIC) protocol - a hardware mechanism for direct communication between register sets of processor cores in a chip multiprocessor running speculative threads. The intended performance improvement over the baseline protocol is in reducing idle waiting of consumer threads by aggressive, speculative forwarding of register values. Software support that enables the identification of threads from a sequential binary code in loop-intensive applications is described first. Then, the enhanced SIC infrastructure is presented. The protocol actions during producer-initiated and consumer-initiated communication between threads are defined as well. Finally, a brief qualitative comparison to baseline SIC protocol is given