On the FPGA Implementation of HAVAL Hash Function

Security is a very important issue, which has attracted the interest of the research community the latest years, at a great factor. Hash functions belong to the category of encryption algorithms. In this work, a novel architecture and the VLSI implementation of HAVAL hash function is proposed. In the proposed architecture, the output length is combined with the number of transformation passes, and in this way fifteen choices for practical applications, are provided. The FPGA synthesis results of the proposed architecture are compared with other related integrations. The proposed architecture achieves high speed performance with low allocated resources