DocumentCode
1916183
Title
An on-chip detection circuit for the verification of IC supply connections
Author
Manhaeve, Hans ; Kerckenaere, Stefaan
Author_Institution
Q-Star Test nv, Brugge, Belgium
fYear
2001
fDate
2001
Firstpage
57
Lastpage
65
Abstract
Presents a noninvasive, highly reliable, testable and (boundary) scan controllable on-chip CMOS current monitor, suited for the validation of IC and module connections and its application at SOC, board and system level. The monitor provides a solution to the problem of verifying the multiple power and ground connections, required to assure a proper power distribution to today´s complex designs. These connections are very difficult to verify as they are connected in parallel and hence a failing connection will only marginally affect the overall connection characteristics but will affect a device´s reliability. The application of the monitor described is an alternative and improvement to the currently used optical. X-ray and other inspection techniques. The monitor presented is designed such that it is fully transparent, testable, guarantees a proper detection, irrespective of local and global process parameter variations -avoiding the need for calibrationand can be put in a power down mode. The application of the monitor is based on the detection of a current flowing through the tested connection, thereby exploiting the inherent resistance of the connection. The sensor can easily be merged to different technologies without making major changes, which makes it well suited for intellectual property re-use
Keywords
CMOS integrated circuits; application specific integrated circuits; boundary scan testing; design for testability; industrial property; integrated circuit testing; CMOS current monitor; DFT; IC supply connections; SOC; boundary scan controllable; global process parameter; intellectual property re-use; multiple ground connections; multiple power connections; on-chip detection circuit; power distribution; power down mode; system level; Application specific integrated circuits; CMOS integrated circuits; Circuit testing; Condition monitoring; Control systems; Integrated circuit testing; Power distribution; Power system reliability; System testing; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on
Conference_Location
San Francisco, CA
ISSN
1550-5774
Print_ISBN
0-7695-1203-8
Type
conf
DOI
10.1109/DFTVS.2001.966752
Filename
966752
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