Combined Test Data Compression and Abort-on-Fail Testing

The increasing test data volume needed for the testing of system-on-chips (SOCs) leads to high automatic test equipment (ATE) memory requirement and long test application times. Scheduling techniques where testing can be terminated as soon as a fault appears (abort-on-fail) as well as efficient compression schemes to reduce the ATE memory requirement have been proposed separately. Previous test data compression architectures often make use of multiple input signature response analyzers (MISRs) for response compression. Therefore, abort-on-fail testing and diagnostic capabilities are limited. In this paper, we propose an SOC test architecture that (1) allows test data compression, (2) where clock cycle based as well as pattern-based abort-on-fail testing are allowed and (3) diagnostic capabilities are not reduced. We have performed experiments on ISCAS designs