Optimisation of High Voltage (1200 V) MOS Transistor: Voltage Handling Capabilities and Switching Behaviour

The goal of this paper is to present some design rules for a high voltage, up to 1200 V, Vertical Double diffused MOS (VDMOS) transistor using a semi-resistive field plate (such as SIPOS: Semi-Insulating POlycrystalline Silicon) as a termination technique and as a passivation. The evolution of breakdown voltage versus critical parameters, such as epitaxial doping and thickness, field plate length and oxide thickness are determined using bidimensionnal simulation. We will present some of these results in this communication. Moreover, the dynamic behaviour of the SIPOS passivated VDMOS will be analysed based on a circuit model of the termination structure; it will be shown that a simple resistive model of the SIPOS layer could not account for the excellent switching speed of the devices, neither for the efficiency of the termination technique at High dV/dt. On the other hand, a distributed resistor/capacitor network will be sufficient to explain these points.