Title :
Analyzing BIST robustness
Author :
Sosnowski, Janusz
Author_Institution :
Inst. of Comput. Sci., Warsaw Univ. of Technol.
Abstract :
Deals with the problem of fault detection and fault handling robustness in BIST schemes. In particular we analyze the susceptibility of signature analyzers to internal faults. Various fault models (black box) within the analyzer circuitry are taken into account. Moreover we check fault impact on software procedures related to BIST and error handling mechanisms using software implemented fault injector
Keywords :
VLSI; built-in self test; error handling; fault simulation; integrated circuit testing; logic analysers; BIST robustness; analyzer circuitry; error handling mechanisms; fault detection; fault handling; fault models; internal faults; signature analyzers; software procedures; software-implemented fault injector; Built-in self-test; Fault tolerant systems; Robustness; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7695-1203-8
DOI :
10.1109/DFTVS.2001.966758
