6-bit Flash ADC with Dynamic Element Matching

Previous work have suggested approaches to introduce dynamic element matching (DEM) into the reference net of a flash analog-to-digital converter. No implementations of such circuits have however been reported. In this work the authors evaluate the suitability and estimate the performance enhancements of a recently proposed DEM architecture by using this in the design of a 6-bit Nyquist rate converter. The converter is sent for manufacturing in a 130 nm partially depleted silicon-on-insulator CMOS technology. It was simulated at transistor level in Cadence using the foundry provided BSIM3SOI Eldo models. These simulations yield a maximum sampling frequency of at least 350 MHz. The simulations also indicate a performance improvement in terms of spurious free dynamic range when using dynamic element matching