A PLL-Based Real-Time Adaptation Circuit for Digital Error Correction of a Pipeline A/D Converter

A quickly locking tracking digital phase-locked loop (PLL) has been implemented to train the digital error correction circuitry of an A/D converter. The PLL and the error correction engine are implemented on an FPGA, and the circuitry includes several speed-up techniques and adaptation loops. The training circuit has been tested using a prototype 14-bit, 300 kS/s pipeline A/D converter driven by a clean sinusoid. The correction for the four msb stages was trained, resulting in an average improvement of 10 dB in SFDR, and reducing the remaining INL below the noise floor of the system