DocumentCode
1916385
Title
Built-in self-reconfiguring systems for fault tolerant mesh-connected processor arrays by direct spare replacement
Author
Takanami, Itsuo
Author_Institution
Ichinoseki Nat. Coll. of Technol., Iwate, Japan
fYear
2001
fDate
2001
Firstpage
134
Lastpage
142
Abstract
Gives built-in self-reconfiguring systems for mesh-connected processor arrays with faulty processors (PEs) which are directly replaced by spare PEs on two orthogonal lines at the edges of the arrays or on the diagonal line of the arrays. To do so, using a Hopfield-type neural network model, we present an algorithm for reconstructing the arrays mentioned above and show its efficiency of reconstruction by computer simulations. Next, we show how the algorithm can be realized by a digital neural circuit. The circuit can be embedded in a target processor array to reconstruct quickly the array with faulty PEs without the aid of a host computer. This implies that the proposed systems are effective in enhancing the run-time reliabilities of the processor arrays
Keywords
Hopfield neural nets; VLSI; built-in self test; fault tolerant computing; microprocessor chips; neural chips; neural net architecture; parallel architectures; Hopfield-type neural network model; digital neural circuit; direct spare replacement; fault tolerant mesh-connected processor arrays; faulty processors; orthogonal lines; processor array; run-time reliabilities; self-reconfiguring systems; Fault tolerant systems; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on
Conference_Location
San Francisco, CA
ISSN
1550-5774
Print_ISBN
0-7695-1203-8
Type
conf
DOI
10.1109/DFTVS.2001.966762
Filename
966762
Link To Document