DocumentCode :
1916508
Title :
Efficient parity prediction in FPGA
Author :
Ko, Seok-Bum ; Xia, Tian ; Lo, Jien-Chung
Author_Institution :
Dept. of Electr. & Comput. Eng., Rhode Island Univ., Kingston, RI, USA
fYear :
2001
fDate :
2001
Firstpage :
176
Lastpage :
181
Abstract :
We propose, in this paper, XOR-based decomposition methods to implement parity prediction circuits efficiently in field programmable gate arrays (FPGAs). The first proposed method is an extension of the Shannon´s expansion theorem. Such extension enables us to force decomposing the parity prediction circuit into appropriate size sub-circuits. The second proposed method is based on the Reed-Muller canonical form that transforms AND/OR Boolean functions to AND/XOR functions. The XOR relation enables us to find more efficient grouping for the parity prediction function. The MCNC benchmark circuits are used to demonstrate the effectiveness of the proposed techniques
Keywords :
Boolean functions; field programmable gate arrays; parity; AND/OR Boolean function; AND/XOR function; Reed-Muller canonical form; Shannon expansion theorem; XOR decomposition method; field programmable gate array; parity prediction circuit; Fault tolerant systems; Field programmable gate arrays; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on
Conference_Location :
San Francisco, CA
ISSN :
1550-5774
Print_ISBN :
0-7695-1203-8
Type :
conf
DOI :
10.1109/DFTVS.2001.966767
Filename :
966767
Link To Document :
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