DocumentCode
1916609
Title
Idle cycles based concurrent error detection of RC6 encryption, [FPGAs]
Author
Wu, Kaijie ; Karri, Ramesh
Author_Institution
Dept. of Electr. & Comput. Eng., Polytech. Univ., Brooklyn, NY, USA
fYear
2001
fDate
2001
Firstpage
200
Lastpage
205
Abstract
Describes a concurrent error detection (CED) technique that uses idle cycles in a data path to do the re-computation and demonstrate its benefits and drawbacks using RC6 encryption as a case study. The idle cycle based CED has low area overhead and performance penalty while maintaining strong CED capability
Keywords
VLSI; adders; cryptography; data flow graphs; error detection; field programmable gate arrays; CED capability; RC6 encryption; area overhead; concurrent error detection; data path; idle cycles based technique; performance penalty; re-computation; Adders; Bidirectional control; Circuit faults; Clocks; Computer errors; Costs; Cryptography; Fault detection; Redundancy; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on
Conference_Location
San Francisco, CA
ISSN
1550-5774
Print_ISBN
0-7695-1203-8
Type
conf
DOI
10.1109/DFTVS.2001.966771
Filename
966771
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