Improving diagnostic resolution of delay faults in FPGAs by exploiting reconfigurability

Author

Ghosh-Dastidar, Jayabrata ; Touba, Nur A.

Author_Institution

Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA

fYear

2001

fDate

2001

Firstpage

215

Lastpage

220

Abstract

Given an FPGA that has failed to meet its timing specification, techniques are proposed to efficiently diagnose the cause of the faulty behavior. An initial list of suspect configuration logic blocks (CLBs) and interconnects is generated using six-valued fault-free simulation and critical path tracing. The initial list of suspects is then reduced by exploiting the reconfigurability of an FPGA. Experimental results indicate a dramatic reduction in the size of the suspect list

Keywords

delays; fault diagnosis; field programmable gate arrays; integrated circuit testing; logic testing; timing; FPGA; critical path tracing; delay faults; diagnostic resolution improvement; faulty behavior diagnosis; reconfigurability; six-valued fault-free simulation; suspect configuration logic blocks; suspect interconnects; timing specification; Circuit faults; Circuit simulation; Circuit testing; Clocks; Delay; Fault diagnosis; Field programmable gate arrays; Integrated circuit interconnections; Logic; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on

Conference_Location

San Francisco, CA

ISSN

1550-5774

Print_ISBN

0-7695-1203-8

Type

conf

DOI

10.1109/DFTVS.2001.966773

Filename

966773