Title :
A low-cost hardware approach to dependability validation of IPs
Author_Institution :
TIMA Lab., Grenoble, France
Abstract :
It has been recognized that analyzing at an early stage of the design the potential faulty behaviors of a circuit becomes a major concern due to the increasing probability of transient faults. It has been proposed to carry out such an analysis using fault injections in a hardware prototype of the circuit under design. This paper reports on a low cost environment using such a flow. A simple FPGA-based development board is used to emulate the circuit and the execution results are analysed on a PC computer. A generic, scalable, approach is proposed to overcome the limitations of such a simple set-up. Such an environment can for example allow a designer to perform efficient and low cost dependability analyses for IP blocks
Keywords :
fault diagnosis; field programmable gate arrays; hardware description languages; industrial property; logic CAD; network routing; FPGA-based development board; IP blocks; circuit under design; dependability validation; fault injections; low-cost hardware approach; potential faulty behaviors; probability; re-usable components; transient faults; Circuit faults; Circuit simulation; Costs; Electrical capacitance tomography; Emulation; Field programmable gate arrays; Hardware; Prototypes; System-on-a-chip; Transient analysis;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7695-1203-8
DOI :
10.1109/DFTVS.2001.966776
