Design of fault-secure encoders for a class of systematic error correcting codes

Author

Piestrak, Stanisloaw J. ; Dandache, Abbas ; Monteiro, Fabrice

Author_Institution

Inst. of Eng. Cybern., Wroclaw Univ. of Technol., Poland

fYear

2001

fDate

2001

Firstpage

314

Lastpage

319

Abstract

In this paper, we consider the open problem of designing fault-secure encoders for various systematic error correcting codes (ECCs). The main idea relies on generating in parallel both the error correcting and detecting check bits. Then, the latter are compared against error detecting check bits which are regenerated from the former. The complexity evaluation of FPGA implementations of encoders with various degrees of parallelism shows that fault-secure versions compare favorably against their unprotected counterparts both with respect to complexity and the maximal frequency of operation

Keywords

circuit complexity; encoding; error correction codes; fault tolerant computing; field programmable gate arrays; logic design; parallel processing; FPGA implementations; complexity evaluation; error correcting bits; error detecting check bits; fault-secure encoder design; maximum operation frequency; parallelism; systematic ECCs; systematic error correcting codes; Character generation; Error correction codes; Fault tolerant systems; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on

Conference_Location

San Francisco, CA

ISSN

1550-5774

Print_ISBN

0-7695-1203-8

Type

conf

DOI

10.1109/DFTVS.2001.966784

Filename

966784