An efficient hardware implementation of H.264 TQ/IQT module

Author

Loukil, H. ; Ben Atitallah, A. ; Kadionik, P. ; Masmoudi, N.

Author_Institution

Nat. Sch. of Eng., Univ. of Sfax, Sfax, Tunisia

fYear

2010

fDate

11-12 Nov. 2010

Firstpage

337

Lastpage

340

Abstract

This paper proposes an efficient hardware architecture for H.264 integer transform, quantization, inverse quantization and integer transform module (TQ/IQT). The TQ/IQT architecture can be used for intra 16×16, intra 4×4 and inter prediction modes. It was described in VHDL and was validated and prototyped using a Altera Stratix II FPGA. The design operates at a maximum frequency of 270 MHz and achieves a throughput from 393 to 1686 Msamples/s depending of the prediction mode, permitting its use in H.264/AVC standard directed to HDTV.

Keywords

data compression; field programmable gate arrays; hardware description languages; high definition television; inverse transforms; video coding; Altera Stratix II FPGA; H.264 TQ-IQT module; H.264-AVC standard; HDTV; VHDL; frequency 270 MHz; hardware architecture; hardware implementation; integer transform module; interprediction mode; inverse quantization; Automatic voltage control; Clocks; Computer architecture; HDTV; Hardware; Quantization; Transforms; FPGA; H.264/AVC; Intra and inter prediction mode; VHDL;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics and Telecommunications (ISETC), 2010 9th International Symposium on

Conference_Location

Timisoara

Print_ISBN

978-1-4244-8457-7

Type

conf

DOI

10.1109/ISETC.2010.5679248

Filename

5679248