Title :
CMOS standard cells characterization for defect based testing
Author :
Pleskacz, Witold A. ; Kasprowicz, Dominik ; Oleszczak, Tomasz ; Kuzmicz, Wieslaw
Author_Institution :
Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Poland
Abstract :
This paper extends the CMOS standard cells characterization methodology for defect based testing. The proposed methodology allows to find the types of faults which may occur in a real IC, to determine their probabilities, and to find the input test vectors which detect these faults. For shorts at the inputs two types of cell simulation conditions - "Wired-AND" and "Wired-OR" are used. Examples of industrial standard cells characterization indicate that a single logic fault probability table is not sufficient. Separate tables for " Wired-AND " and " Wired-OR" conditions at the inputs are needed for full characterization and hierarchical test generation
Keywords :
CMOS logic circuits; cellular arrays; fault simulation; integrated circuit testing; logic testing; CMOS IC; Wired-AND simulation; Wired-OR simulation; defect testing; fault detection; hierarchical test vector generation; logic fault probability table; standard cell; CMOS digital integrated circuits; Circuit faults; Circuit testing; Computational modeling; Digital circuits; Integrated circuit modeling; Integrated circuit testing; Probabilistic logic; Semiconductor device modeling; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7695-1203-8
DOI :
10.1109/DFTVS.2001.966792
