High-level modeling of a high-speed flash A/D converter for mixed-signal simulations of digital telecommunication front-ends

Author

Compiet, J. ; de Jong, P. ; Wambacq, P. ; Vandersteen, G. ; Donnay, S. ; Engels, M. ; Bolsens, I.

Author_Institution

IMEC, Leuven, Belgium

fYear

2000

fDate

2000

Firstpage

135

Lastpage

140

Abstract

A hierarchical high-level model of a high-speed flash ADC is presented. The input parameter list is extracted from a 400 MHz, 4-bit, flash ADC designed in HSPICE in a 0.35 μm CMOS technology. A speedup in simulation time of 5000 is reported compared to the 3-bit flash ADC HSPICE simulations. The accuracy of the model is verified with HSPICE simulations and shows a good agreement

Keywords

CMOS integrated circuits; analogue-digital conversion; circuit simulation; equivalent circuits; high-speed integrated circuits; integrated circuit modelling; mixed analogue-digital integrated circuits; telecommunication equipment; 0.35 micron; 4 bit; 400 MHz; C++ model; HSPICE simulations; digital telecommunication front-ends; flash A/D converter; hierarchical high-level model; high-level modeling; high-speed flash ADC; input parameter list extraction; mixed-signal simulations; Analog-digital conversion; CMOS process; CMOS technology; Capacitors; Computational Intelligence Society; Encoding; Poles and zeros; Quantization; Sampling methods; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium on

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5975-5

Type

conf

DOI

10.1109/SSMSD.2000.836461

Filename

836461