Title :
Functional-based ATPG for path delay faults
Author :
Michael, M. ; Tragoudas, S.
Author_Institution :
Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
Abstract :
A novel methodology for non-enumerative ATPG for path delay faults is presented. Tests are generated by manipulating, in a systematic yet simple way, sets of pairs of functions. Each pair of functions represents the constraints to be satisfied by the non-enumerative delay fault test for each time frame of a transition. A test that detects many faults is generated from each pair of functions. A current ROBDD-based implementation of this technique is used to analyze the delay fault testability of the ISCAS´85 benchmark circuits
Keywords :
automatic test pattern generation; binary decision diagrams; delays; integrated circuit testing; logic testing; ROBDD-based implementation; delay fault testability analysis; functional-based ATPG; non-enumerative ATPG; path delay faults; reduced-order BDD; Automatic test pattern generation; Benchmark testing; Boolean functions; Circuit faults; Circuit testing; Data structures; Delay effects; Electrical fault detection; Fault detection; System testing;
Conference_Titel :
Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5975-5
DOI :
10.1109/SSMSD.2000.836465
